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W3HG2128M72ACER-AD6 may 2006 rev. 5 preliminary* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 2gb C 2x128mx72 ddr2 sdram registered, w/pll, vlp description the w3hg2128m72acer is a 2x128mx72 double data rate ddr2 sdram high density module based on ddr2 sdram components. this memory module consists of eighteen stacks of 256mx4 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 240-pin dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option ? parity function features 240-pin, dual in-line very low pro? le (vlp) memory module fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4300 and pc2-3200 utilizes 800, 667, 533 and 400 mb/s ddr2 sdram components v cc = v ccq = 1.8v v ccspd = +1.7v to +3.6v differential data strobe (dqs, dqs#) option four-bit prefetch architecture dll to align dq and dqs transitions with ck multiple internal device banks for concurrent operation supports duplicate output strobe (rdqs/rdqs#) programmable cas# latency (cl): 3, 4, 5 and 6 adjustable data-output drive strength on-die termination (odt) posted cas# additive latency: 0, 1, 2, 3 and 4 serial presence detect (spd) with eeprom 64ms: 8,192 cycle refresh gold edge contacts ecc error detection and correction dual rank rohs compliant package option ? 240 pin vlp: 18.29mm (0.720") typ operating frequencies pc2-3200 pc2-4300 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 * consult factory for availability
W3HG2128M72ACER-AD6 preliminary 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 61 a4 121 v ss 181 v ccq 2v ss 62 v ccq 122 dq4 182 a3 3 dq0 63 a2 123 dq5 183 a1 4 dq1 64 v cc 124 v ss 184 v cc 5v ss 65 v ss 125 dqs9 185 ck0 6 dqs0# 66 v ss 126 dqs9# 186 ck0# 7dqs067 v cc 127 v ss 187 v cc 8v ss 68 nc/par_in 128 dq6 188 a0 9 dq2 69 v cc 129 dq7 189 v cc 10 dq3 70 a10/ap 130 v ss 190 ba1 11 v ss 71 ba0 131 dq12 191 v ccq 12 dq8 72 v ccq 132 dq13 192 ras# 13 dq9 73 we# 133 v ss 193 s0# 14 v ss 74 cas# 134 dqs10 194 v ccq 15 dqs1# 75 v ccq 135 dqs10# 195 odt0 16 dqs1 76 s1# 136 v ss 196 a13 17 v ss 77 odt1 137 nc 197 v cc 18 reset# 78 v ccq 138 nc 198 v ss 19 nc 79 v ss 139 v ss 199 dq36 20 v ss 80 dq32 140 dq14 200 dq37 21 dq10 81 dq33 141 dq15 201 v ss 22 dq11 82 v ss 142 v ss 202 dqs13 23 v ss 83 dqs4# 143 dq20 203 nc/dqs13# 24 dq16 84 dqs4 144 dq21 204 v ss 25 dq17 85 v ss 145 v ss 205 dq38 26 v ss 86 dq34 146 dqs11 206 dq39 27 dqs2# 87 dq35 147 dqs11# 207 v ss 28 dqs2 88 v ss 148 v ss 208 dq44 29 v ss 89 dq40 149 dq22 209 dq45 30 dq18 90 dq41 150 dq23 210 v ss 31 dq19 91 v ss 151 v ss 211 dqs14 32 v ss 92 dqs5# 152 dq28 212 nc/dqs14# 33 dq24 93 dqs5 153 dq29 213 v ss 34 dq25 94 v ss 154 v ss 214 dq46 35 v ss 95 dq42 155 dqs12 215 dq47 36 dqs3# 96 dq43 156 dqs12# 216 v ss 37 dqs3 97 v ss 157 v ss 217 dq52 38 v ss 98 dq48 158 dq30 218 dq53 39 dq26 99 dq49 159 dq31 219 v ss 40 dq27 100 v ss 160 v ss 220 nc 41 v ss 101 sa2 161 cb4 221 nc 42 cb0 102 nc 162 cb5 222 v ss 43 cb1 103 v ss 163 v ss 223 dqs15 44 v ss 104 dqs6# 164 dqs17 224 nc/dqs15# 45 dqs8# 105 dqs6 165 dqs17# 225 v ss 46 dqs8 106 v ss 166 v ss 226 dq54 47 v ss 107 dq50 167 cb6 227 dq55 48 cb2 108 dq51 168 cb7 228 v ss 49 cb3 109 v ss 169 v ss 229 dq60 50 v ss 110 dq56 170 v ccq 230 dq61 51 v ccq 111 dq57 171 cke1 231 v ss 52 cke0 112 v ss 172 v cc 232 dqs16 53 v cc 113 dqs7# 173 nc 233 nc/dqs16# 54 nc 114 dqs7 174 nc 234 v ss 55 nc/err_out 115 v ss 175 v ccq 235 dq62 56 v ccq 116 dq58 176 a12 236 dq63 57 a11 117 dq59 177 a9 237 v ss 58 a7 118 v ss 178 v cc 238 v cc spd 59 v cc 119 sda 179 a8 239 sa0 60 a5 120 scl 180 a6 240 sa1 pin names pin name function a0-a13 address inputs ba0,ba1 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes dqs0#-dqs8# data strobes complement dm0-dm8 data masks dqs9#-dqs17# data strobe negative dqs9-dqs17 data strobe odt0, odt1 on-die termination control ck0,ck0# clock inputs, positive line cke0, cke1 clock enables s0#, s1# chip selects ras# row address strobe cas# column address strobe we# write enable reset# register reset input sa0-sa2 spd address sda spd data input/output scl serial presence detect(spd) clock input v cc core power (1.8v) v ccq i/o power (1.8v) v ss ground v ref power supply for reference v cc spd spd power nc spare pins, no connect
W3HG2128M72ACER-AD6 preliminary 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 functional block diagram a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ccspd v cc /v ccq v ref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams p l l oe ck0 ck0# reset#** pck0-pck6, pck8, pck9 ck : ddr2 sdrams pck0#-pck6#, pck8#, pck9# ck# : ddr2 sdrams pck7 ck : register pck7# ck# : register vss rs0# dqs0 dqs0# cs# dm dqs dqs# dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 dqs9 dqs9# dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 dqs1 dqs1# dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 dqs10 dqs10# dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 dqs2 dqs2# dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 dqs11 dqs11# dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 dqs3 dqs3# dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 dqs12 dqs12# dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 dqs5 dqs5# dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 dqs14 dqs14# dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 dqs4 dqs4# dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 dqs13 dqs13# dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 dqs6 dqs6# dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 dqs15 dqs15# dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 dqs8 dqs8# cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 dqs17 dqs17# cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 dqs#7 dqs7# dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 dqs16 dqs16# dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 i/o 0 i/o 1 i/o 2 i/o 3 rs1# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# cs# dm dqs dqs# 1:2 r e g i s t e r rst# s1# ba0-ba1 a0-a13 ras# cas# we# cke0 cke1 reset# pck7** pck7#** rs1# cs# : ddr2 sdrams rba0-rba1 ba0-ba1 : ddr2 sdrams ra0-ra13 a0-a13 : ddr2 sdrams rras# ras# : ddr2 sdrams rcas# cas# : ddr2 sdrams rwe# we# : ddr2 sdrams rcke0 cke : ddr2 sdrams rcke1 cke : ddr2 sdrams odt0 odt1 rodt0 odt : ddr2 sdrams rodt1 odt : ddr2 sdrams s0# rs0# cs# : ddr2 sdrams note: all resistor values are 22 ohms unless otherwise speci? ed.
W3HG2128M72ACER-AD6 preliminary 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 recommended dc operating conditions all voltages referenced to v ss parameter symbol rating units notes min. type max. supply voltage v cc 1.7 1.8 1.9 v 4 supply voltage for dll v ccl 1.7 1.8 1.9 v 4 supply voltage for output v ccq 1.7 1.8 1.9 v 4 input reference voltage v ref 0.49*v ccq 0.50*v ccq 0.51*v ccq v 1, 2 termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 there is no speci? c device v cc supply voltage requirement for sstl-1.8 compliance. however under all conditions v ccq must be less than or equal to v cc . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ccq of the transmitting device and v ref is expected to track variations in v ccq . 2. peak to peak ac noise on v ref may not exceed 2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. v cc , v ccq and v cc l are tied together on this module. absolute maximum ratings sstl_1.8v symbol parameter rating units notes v cc voltage on v cc pin relative to v ss - 1.0 v - 2.3 v v 5 v ccq voltage on v ccq pin relative to v ss - 0.5 v - 2.3 v v 5 v ccl voltage on v ccl pin relative to v ss - 0.5 v - 2.3 v v 5 v in , v out voltage on any pin relative to v ss - 0.5 v - 2.3 v v 5 t stg storage temperature -55 to +100 c 5, 6 5. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 6. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. capacitance t a = 25c, f = v ref = gnd, f = 100mhz, v cc = v ccq = 1.8v parameter symbol max units input capacitance: ck, ck# c ck 5.6 pf input capacitance: cke, cs# ci 1 12.4 pf input capacitance: addr. ras#, cas#, we#, odt ci 2 12.4 pf input/output capacitance: dq, dqs, dm, dqs#, cb ci o 15.6 pf
W3HG2128M72ACER-AD6 preliminary 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 ddr2 i cc specifications and conditions includes ddr2 sdram components only symbol proposed conditions 806 665 534 403 units i cc0 operating one bank active-precharge current; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,720 1,530 1,530 ma i cc1 operating one bank active-read-precharge current; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ), t rcd = t rcd (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w tbd 1,980 1,800 1,710 ma i cc2p precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 180 180 180 ma i cc2q precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 1,800 1,440 1,260 ma i cc2n precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are switching; data bus inputs are switching tbd 1,980 1,620 1,440 ma i cc3p active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 1,260 1,080 900 ma slow pdn exit mrs(12) = 1 tbd 360 360 360 ma i cc3n active standby current; all banks open; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 2,340 1,980 1,620 ma i cc4w operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 2,880 2,430 2,070 ma i cc4r operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w tbd 3,240 2,700 2,160 ma i cc5b burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 7,560 7,200 6,840 ma i cc6 self refresh current; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating tbd 180 180 180 ma i cc7 operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data pattern is same as i cc4r ; refer to the following page for detailed timing conditions tbd 5,130 4,770 4,230 ma note: i cc specs are based on micron components. other dram manufacturers parameters may be different.
W3HG2128M72ACER-AD6 preliminary 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 ac timing parameters 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 667 534 403 parameter symbol min max min max min max min max unit notes clock clock cycle time cl = 6 t ck (6) tbd tbd ps 16, 24 cl = 5 t ck (5) tbd tbd 3,000 8,000 ps 16, 24 cl = 4 t ck (4) tbd tbd 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24 cl = 3 t ck (3) tbd tbd 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24 ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck 18 ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck 18 half clock period t hp tbd tbd min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps 19 data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac (max) t ac max t ac max ps 8, 9 data-out low-impedance window from ck/ck# t lz tbd tbd t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) ps 8, 10 dq and dm input setup time relative to dqs t dsa tbd tbd 300 350 400 ps 7, 15, 21 dq and dm input hold time relative to dqs t dha tbd tbd 300 350 400 ps 7, 15, 21 dq and dm input setup time relative to dqs t dsb tbd tbd 100 100 150 t ck 7, 15, 21 dq and dm input hold time relative to dqs t qhb tbd tbd 175 225 275 ps 7, 15, 21 dqdqs hold, dqs to ? rst dq to go nonvalid, per access relative to dqs t dipw tbd tbd 0.35 0.35 0.35 ps data hold skew factor t qhs tbd tbd 340 400 450 dqCdqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs 15, 17 data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq 15, 17 data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck risingC setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising C hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqsCdq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps 15, 17 dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck 35 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
W3HG2128M72ACER-AD6 preliminary 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 ac timing parameters (continued) 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit notes data strobe dqs read preamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck 35 dqs write preamble setup time t wpres tbd tbd 0 0 0 ps 12, 13, 36 dqs write preamble t wpre tbd tbd 0.35 0.25 0.25 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck 11 write command to ? rst dqs latching transition t dqss tbd tbd wl- 0.25 wl- 0.25 wl- 0.25 t ck command and address address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t isa tbd tbd 400 500 600 ps 6, 21 address and control input hold time t iha tbd tbd 400 500 600 ps 6, 21 address and control input setup time t isb tbd tbd 200 250 350 ps 6, 21 address and control input hold time t ihb tbd tbd 275 375 475 ps 6, 21 cas# to cas# command delay t ccd tbd tbd 222t ck active to active (same bank) command t rc tbd tbd 55 55 55 ns 33 active bank a to active b bank command t rrd tbd tbd 7.5 7.5 7.5 ns 27 active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 ns 30 active to precharge command t ras tbd tbd 40 70,000 40 70,000 40 70,000 ns 20, 33 internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns 23, 27 write recovery time t wr tbd tbd 15 15 15 ns 27 auto precharge write recovery and precharge time t dal tbd tbd t wr +t rp t wr +t rp t wr +t rp ns 22 interval write to read command delay t wtr tbd tbd 10 7.5 10 ns 27 precharge command period t rp tbd tbd 15 15 15 ns 31 precharge all command period t rpa tbd tbd t rp +t ck t rp +t ck t rp +t ck ns 31 load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is +t ck+ t ih t is +t ck+ t ih t is +t ck+ t ih ns 28 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
W3HG2128M72ACER-AD6 preliminary 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 ac timing parameters (continued) 0c t case < +85c; v ccq = + 1.8v 0.1v, v cc = +1.8v 0.1v ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit notes self refresh refresh to active or refresh to refresh command interval t rfc (2gb) tbd tbd 105 70,000 105 70,000 105 70,000 ns 14 t rfc (4gb) tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns 14 average periodic refresh interval t refi tbd tbd 200 7.8 7.8 7.8 s 14 exit self refresh to non-read command t xsnr tbd tbd t rfc (min) +10 t rfc (min) +10 t rfc (min) +10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference t isxr tbd tbd t is t is t is ps 6, 29 odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac(min) t ac(max) +700 t ac(min) t ac(max) +1,000 t ac(min) t ac(max) +1,000 ps 25 odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 t ac(min) t ac(max) +600 ps 26 odt turn-on (power-down mode) t aonpd tbd tbd t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ac(min) +2,000 2x t ck + t ac (max) + 1,000 t ck odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7-al 6-al 6-al t ck exit precharge power-down to any non-read command. t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck 34 note: ? ac speci? cation is based on micron components. other dram manufactures speci? cation may be different.
W3HG2128M72ACER-AD6 preliminary 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 notes 1. all voltages referenced to v ss 2. tests for ac timing, i cc, and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: 4. ac timing and i cc tests may use a v il to v ih swing of up to 1.0v in the test environment parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew derates less than 1.0v/ns require the timing parameters to be rated as speci? ed. 5. the ac and dc input level speci? cations are as de? ned in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate is at 1.0v/ns. command/address input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated using t isb and the setup and hold time derating values table. t is timing (t isb) is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal. t ih timing (t ihb ) is referenced from v ih (ac) for a rising signal and v il (dc) for a falling signal. the timing table also lists the t isb and t ihb values for a 1.0v/ns slew rate; these are the base values. 7. data minimum input slew rate is at 1.0v/ns. data input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated if the timing is referenced from the logic trip points. t ds timing (t dsb ) is referenced from v ih (ac) for a rising signal and v il (ac) for a falling signal. t ih timing (t ihb ) is referenced from v ih (dc) for a rising signal and v il (dc) for a falling signal. the timing table lists the t ds b and t dh b values for a 1.0v/ns slew rate. if the dqs/dqs# differential strobe feature is not enabled, timing is no longer referenced to the cross point of dqs/dqs#. data timing is now referenced to v ref , provided the dqs slew rate is not less than 1.0v/ns. if the dqs slew rate is less than 1.0v/ns, then data timing is now referenced to v ih (ac) for a rising dqs and v il (dc) for a falling dqs. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (when the device output is no longer driving (t hz ) or begins driving (t lz ). 9. this maximum value is derived from the referenced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) t lz will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the dont care state after completion of the postamble is the dqs-driven signal should either be high, low or output (v out ) reference point 25? v tt = v cc q/2 high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transitions high (above v ih dc (min) then it must not transition low (below v ih (dc) prior to t dqsh (min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turn around. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8192 refresh commands must be issued every 64ms. 15. each half-byte lane has a corresponding dqs. 16. ck and ck# input slew rate must be 1v/ns ( 2v/ns if measured differentially). 17. the data valid window is derived by achieving other speci? cations - t hp . (t ck /2), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum speci? cation limits for t cl and t ch . for example, t cl and t ch are = 50 percent of the period, less the half period jitter [t jit (hp)] of the clock source, and less the half period jitter due to cross talk [t jit (cross talk)] into the clock traces. 19. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. 20. reads and writes with auto precharge are allowed to be issued before tras (min) is satis? ed since t ras lockout feature is supported in ddr2 sdram devices. 21. v il /v ih ddr2 overshoot/undershoot. refer to the 512mb or 1gb ddr2 sdram data sheet for more detail. 22. t dal = (nwr) + (t rp /t ck ): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for 534 at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75ns) clock = 4 + (4) clocks = 8 clocks. 23. the minimum read to internal precharge time. this parameter is only applicable when t rtp /2*t ck ) > 1. if t rtp /2*t ck ) 1, then equation al + bl/2 applies. notwithstanding, t ras (min) has to be satis? ed as well. the ddr2 sdram device will automatically delay the internal precharge command until t ras (min) has been satis? ed. 24. operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. 25. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond .
W3HG2128M72ACER-AD6 preliminary 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 26. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are measured from t aofd . 27. this parameter has a two clock minimum requirement at any t ck . 28. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. 29. t isxr is equal to t is and is used for cke setup time during self refresh exit. 30. no more than 4 bank active commands may be issued in a given t faw (min) period. t rrrd (min) restriction still applies. the t faw (min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks already open or closed. 31. t rpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or closed. if a single-bank precharge command is issued, t rp timing applies. t rpa (min) applies to all 8-bank ddr2 devices. 32. value is minimum pulse width, not the number of clock registrations. 33. applicable to read cycles only. write cycles generally require additional time due to write recovery time (t wr ) during auto precharge. 34. t cke (min) of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2* t ck + t ih . 35. this parameter is not referenced to a speci? c voltage level, but speci? ed when the device output is no longer driving (t rpst ) or beginning to drive (t rpre ). 36. when dqs is used single-ended, the minimum limit is reduced by 100ps.
W3HG2128M72ACER-AD6 preliminary 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 1.27 (0.050 -0.004) 4.06 (0.160) 133.35 (5.25) front view back view 4.00 (0.157) 3.00 (0.118) 18.29 (0.720) typ 2.50 0.20 (0.098 0.007) 1.50 0.10 (0.059 0.004) 4.00 (0.157) 5.00 (0.196) 63.00 (2.48) 55.00 (2.165) 1.00 (0.039) 0.80 0.05 (0.031 0.002) package dimensions for ad6 * all dimensions are in millimeters and (inches) ordering information for ad6 part number speed/data rate cas latency t rcd t rp height* w3hg2128m72acer806ad6xg** 400mhz/800mb/s 6 6 6 18.29mm (0.72") typ w3hg2128m72acer665ad6xg** 333mhz/667mb/s 5 5 5 18.29mm (0.72") typ w3hg2128m72acer534ad6xg 266mhz/533mb/s 4 4 4 18.29mm (0.72") typ w3hg2128m72acer403ad6xg 200mhz/400mb/s 3 3 3 18.29mm (0.72") typ ** contact factory for availability notes: ? rohs compliant product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
W3HG2128M72ACER-AD6 preliminary 12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 part numbering guide w 3 h g 2 128m 72 a c e r xxx ad6 x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width x4 stacked die bga 1.8v registered speed (mb/s) package 240 pin (.72) component vendor name (m = micron) (s = samsung) g = rohs compliant
W3HG2128M72ACER-AD6 preliminary 13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs may 2006 rev. 5 document title 2gb C 2x128mx72 ddr2 sdram registered, w/pll,vlp revision history rev # history release date status rev 0 evaluation and review july 2005 concept rev 1 1.1 created concept data sheet december 2005 concept rev 2 2.1 added i cc specs 2.2 added ac specs december 2005 advanced rev 3 3.1 moved to preliminary january 2006 preliminary rev 4 4.0 updated package outline 4.1 added "stacked die" designation "c" to part number and part number guide 4.2 added new capacitance numbers. february 2006 preliminary rev 5 5.1 corrected package width dimension may 2006 preliminary

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